Shenzhen Fiano Electronic Technology Co. Ltd
Shenzhen Fiano Electronic Technology Co. Ltd
512MB to 2GB DDR Laptop/Computer Memory RAM with 533/667/800Mbps Data Rate
  • 512MB to 2GB DDR Laptop/Computer Memory RAM with 533/667/800Mbps Data Rate
512MB to 2GB DDR Laptop/Computer Memory RAM with 533/667/800Mbps Data Rate

512MB to 2GB DDR Laptop/Computer Memory RAM with 533/667/800Mbps Data Rate

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Basic Info
Basic Info
Payment Type: Western Union, PayPal, T/T, MoneyGram or Cash
Product Description
Product Description
  • Specifications:
    • Capacity: 512MB to 2GB DDR 333/400 and DDR2 533/667/800MHz
    • 168/184/240-pin socket type dual-in line memory module (DIMM)
    • Data rate: 533/667/800Mbps (maximum)
    • 2.5V (SSTL-2 compatible) I/O for DDR products, 1.8V power supply for DDR2 products
    • Chipset organization: 64 x 8, 128 x 4 and 128 x 8
    • Double-data-rate architecture, two data transfers per clock cycle
    • Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at receiver
    • Data input and output are synchronized with DQS
    • DQS is edge aligned with data for read, center aligned with data for write
    • Various clock input (CK and CK)
    • DLL align DQ and DQS transitions with CK transitions
    • Brands of chipset: ELPIDA, Mosel and Nanya
    • Four internal banks for concurrent operating (component)
    • Posted CAS by programmable additive latency for better command and data bus efficiency
    • Programmable burst length: 2, 4 and 8
    • Programmable/CAS latency (CL): 3
    • Refresh cycles: 8192 refresh cycles/64ms
    • 2 variation of refresh: auto-refresh and self refresh
    • 7.8US maximum average periodic refresh interval
  • Capacity: 512MB to 2GB DDR 333/400 and DDR2 533/667/800MHz
  • 168/184/240-pin socket type dual-in line memory module (DIMM)
  • Data rate: 533/667/800Mbps (maximum)
  • 2.5V (SSTL-2 compatible) I/O for DDR products, 1.8V power supply for DDR2 products
  • Chipset organization: 64 x 8, 128 x 4 and 128 x 8
  • Double-data-rate architecture, two data transfers per clock cycle
  • Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at receiver
  • Data input and output are synchronized with DQS
  • DQS is edge aligned with data for read, center aligned with data for write
  • Various clock input (CK and CK)
  • DLL align DQ and DQS transitions with CK transitions
  • Brands of chipset: ELPIDA, Mosel and Nanya
  • Four internal banks for concurrent operating (component)
  • Posted CAS by programmable additive latency for better command and data bus efficiency
  • Programmable burst length: 2, 4 and 8
  • Programmable/CAS latency (CL): 3
  • Refresh cycles: 8192 refresh cycles/64ms
  • 2 variation of refresh: auto-refresh and self refresh
  • 7.8US maximum average periodic refresh interval
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